The present invention relates to a nonvolatile semiconductor memory having a memory cell allowing an electrical data write and erase.
Conventionally, a flash memory which can be erased in blocks has received a great deal of attention as one of electrically programmable and erasable read only memories (EEPROMs) which are classified as one of nonvolatile semiconductor memories. The flash memory cell has a MOS transistor structure wherein a floating gate insulated from the peripheral region is formed between the control gate and the substrate having the channel. Discrimination between data of level "1" and data of level "0" depends on the presence/absence of charges in the floating gate.
Techniques of storing multivalue data in one cell have been conventionally developed. As the first prior art, multivalue data is realized by the circuit operation. In this prior art, the amount of charges to be stored in the floating gate is changed to realize, e.g., quarternary data.
In this case, however, the number of power supplies necessary for realizing multivalue data increases to result in a heavy load on, e.g., a charge pump circuit.
Additionally, to realize multivalue data by the circuit operation, a threshold value range per value must be considerably narrow. For this reason, the amount of charges to be injected into the floating gate must be strictly controlled to result in an increase in load on the controller or write time. This narrow threshold value range also imposes limitations on the margin to a change over time in data holding characteristics to lower reliability. More specifically, when the held charge amount changes along with the elapse of time, the read current changes accordingly, and a data value different from that stored is read.
As the second prior art, in a nonvolatile semiconductor memory, two floating gates and one control gate are arranged in correspondence with one channel (memory cell), and the impurity concentration on the side of the drain continuous to the channel is set to be lower than that on the side of the source continuous to the channel, thereby storing quarternary data in one memory cell (reference 1: Japanese Patent Laid-Open No. 1-212472).
FIG. 6 shows the schematic arrangement of the nonvolatile semiconductor memory. As shown in FIG. 6, in this nonvolatile semiconductor memory, the drain on a semiconductor substrate 701 has an n.sup.+ -type drain region 702 and an n.sup.- -type drain region 709 adjacent to a channel region 704. The channel region 704 is divided into three parts: a channel region 704d near the n.sup.- -type drain region 709, a channel region 704s near a source region 703, and a channel region 704c between the channel region 704d and the channel region 704s.
In this nonvolatile semiconductor memory, two floating gates 706d and 706s are insulated from each other. The floating gate 706d is formed on part of the n.sup.- -type drain region 709 and the channel region 704d via a gate oxide film 705. The floating gate 706s is formed on part of the n.sup.+ -type source region 703 and the channel region 704s via the gate oxide film 705. The channel resistance of the n.sup.- -type drain region 709 is changed by lowering the impurity concentration relative to the n.sup.+ -type drain region 702 or the n.sup.+ -type source region 703.
A control gate 708 is formed on the floating gates 706d and 706s via an insulating film 707 and on the channel region 704c via the gate oxide film 705. The distance between the control gate 708 above the channel region 704c and the semiconductor substrate 701 is almost the same as that between the floating gates 706d and 706s and the semiconductor substrate 701.
The operation of the nonvolatile semiconductor memory with the above arrangement will be described next.
A write is performed by selectively injecting electrons into the floating gates 706d and 706s. Electron injection into the drain-side floating gate 706d will be referred to as a write D. Electron injection into the source-side floating gate 706s will be referred to as a write S.
In the write D, a control gate voltage VG of 12.5 V and a drain voltage VD of 8 V are applied, and the n.sup.+ -type source region 703 and the semiconductor substrate 701 are grounded. At this time, the channel regions 704d, 704c, and 704s are inverted to flow electrons from the n.sup.+ -type source region 703 to the n.sup.- -type drain region 709. These electrons are accelerated by the voltage between the drain and the source and become hot electrons near the n.sup.- -type drain region 709. The hot electrons are attracted by the electric field of the control gate 708 and injected into the floating gate 706d across the energy gap of the gate oxide film 705. When the electrons are selectively injected into the floating gate 706d, the write D is complete.
On the other hand, in the write S, a control gate voltage VG of 12.5 V and a source voltage VS of 8 V are applied, and the n.sup.+ -type drain region 702 and the semiconductor substrate 701 are grounded. As a result, electrons are selectively injected into the floating gate 706s, as in the above-described case, and the write S is complete.
Even when a voltage of 12.5 V is applied to the memory transistor which has undergone the write D as the control gate voltage VG, and the n.sup.+ -type drain region 702 and the semiconductor substrate 701 are grounded, the channel regions 704d, 704c, and 704s are inverted. When a voltage of 8 V is applied as the source voltage VS, the write S can be performed without damaging the write D, as in the above-described case. This operation will be referred to as a write D & S.
As described above, as the write state of this nonvolatile semiconductor memory, the write D, the write S, or the write D & S can be selected. When a nonwrite state in added, quarternary data is realized.
In this nonvolatile semiconductor memory, however, the quarternary data is determined using the difference in threshold value and the difference in channel resistance between the write states. A threshold value VT corresponds to the control gate voltage VG at which the drain current starts flowing after gradual voltage application to the control gate. The erase state, the write D state, and the write S state have different threshold values VT of 1 V, 2 V, and 3 V, respectively, but equal conductance characteristics. The write S state and the write D & S state have the same threshold value VT of 3 V, though the conductance characteristics beyond the threshold value are different. Therefore, when the control gate voltage VG is 3 V, the write S cannot be discriminated from the write D & S, so only three values are read. To discriminate the write S from the write D & S, the control gate voltage must be set to be higher than 3 V, and 5 V in the second prior art, using the difference in conductance characteristics. That is, to read quarternary data, a high control gate voltage is required.
In addition, since this nonvolatile semiconductor memory requires, under the control electrode, not only the area for the two floating gates but also some area for the channel region 704c having no floating gate, the area of one cell increases.
As the third prior art, there is an other nonvolatile semiconductor memory having two floating gates per cell which are arranged relatively close to each other, unlike the above-described nonvolatile semiconductor memory (reference 2: Japanese Patent Application No. 6-77498).
In this nonvolatile semiconductor memory, source and drain regions 801 and 802 spaced apart from each other by a predetermined distance are formed in the surface layer of a semiconductor substrate 800 consisting of p-type silicon, as shown in FIG. 7. A floating gate 804 consisting of polysilicon is formed on the channel region between the source and drain regions 801 and 802 via a first gate insulating film 803.
The floating gate 804 is divided into two parts along the channel length. A control gate 806 consisting of polysilicon is formed on divided floating gates 804a and 804b via a second gate insulating film 805.
To erase data in the above arrangement, electrons are extracted from the floating gate 804 or injected into the floating gate 804 at once. Alternatively, the floating gate 804 may be irradiated with a UV ray.
On the other hand, to write data, electrons are selectively injected into the source- and drain-side floating gates 804a and 804b by using F-N tunneling or hot electrons.
With the write, the following four states can be obtained. As the first state, electrons are injected into neither the floating gate 804a nor 804b. As the second state, electrons are injected into the floating gate 804a. As the third state, electrons are injected into the floating gate 804b. As the fourth state, electrons are injected into both the floating gates 804a and 804b.
If the floating gates 804a and 804b have different areas, i.e., the threshold voltage of the memory cell transistor changes, quarternary data can be stored in this memory cell.
In this nonvolatile semiconductor memory, however, since a gap is formed between the two floating gates arranged in the source/drain direction, the channel resistance undesirably increases.
As described above, the conventional techniques of realizing multivalue data by the circuit operation have the following problems.
In the first prior art, the number of power supplies necessary for realizing multivalue data increases to result in a heavy load on, e.g., the charge pump circuit.
To realize multivalue data by the circuit operation, the threshold value range per value must be considerably narrow. For this reason, the amount of charges to be injected into the floating gate must be strictly controlled to result in an increase in load on the controller or write time. This narrow threshold value distribution also imposes limitations on the margin to a change over time in data holding characteristics to lower reliability.
In the second prior art, a high control gate is required to read data, as described above. In addition, since the device requires, under the control electrode, not only the area for the two floating gates but also some area for the region having no floating gate, the area of one cell increases.
In the third prior art, the area of one memory cell can be reduced. However, since a gap is present between the two floating gates arranged in the source/drain direction, the channel resistance undesirably increases. For this reason, in the third prior art, the absolute value of the read current becomes small, and the margin between determination currents for multivalue data narrows accordingly, so quarternary data determination by the sense amplifier is difficult.
In the second and third prior arts, the source and the drain are controlled to write data in the two floating gates. This requires a large current for write control. In addition, source-drain or source--source interference between adjacent memory cells must be prevented. For this purpose, adjacent memory cells must be insulated from each other by, e.g., an element isolation region. As a result, high integration is impeded because of necessity of the isolation region.